chip architecture
英 [tʃɪp ˈɑːkɪtektʃə(r)]
美 [tʃɪp ˈɑːrkɪtektʃər]
网络 芯片体系结构; 芯片架构; 了解到其芯片架构
双语例句
- Arm [ a competing mobile chip architecture, used by Qualcomm] is more efficient.
ARM（高通采用的竞争性移动芯片架构）更高效。 - At the point of hardware, the features and capacity of ARM9 and S3C2410 ( a chip based on ARM9 architecture) are introduced, which is the hardware foundation of the whole project.
硬件环境方面介绍了论文工作所用的硬件平台，重点介绍了平台所用的核心&S3C2410（基于ARM9架构）的特点及性能，这是论文工作的硬件基础； - Design and Implementation of Multi-Processor System Based on Net on Chip Architecture
多核系统的片上网络（NoC）架构设计与实现 - Chip architecture is again mirrored in the company itself.
芯片架构再次体现在公司架构上。 - Android also allows most programs to work even if manufacturers change the underlying chip architecture.
即便生产商改变了平板电脑的芯片构架，Android上的大多数程序都能正常工作，而且Google不会向使用Android的公司收费。 - Performance analysis and comparison of shared bus and NoC on chip communication architecture
片上通信结构&共享总线和NoC的分析与比较 - Trusted computing is the new stage of information security. It brings security chip architecture in the computing hardware platform, and the whole system's security is greatly improved correspondingly.
可信计算是信息安全研究的一个新阶段，它通过在计算设备硬件平台上引入安全芯片架构，通过其提供的安全特性来提高整个系统的安全性。 - In this paper, a designing theory and method of cryptogrammic chip based on the reconfigurable architecture is brought forward to improve the security of encryption that is based on the algorithms in existence.
为了在现有算法的基础上提高加密的安全性，提出了一种基于可重组体系结构的密码芯片设计原理和方法。 - And DSP, this kind of chip having a special architecture for some arithmetic, helps us to process some digital signals.
DSP芯片是具有特殊结构的微处理器，是专门为快速实现各种数字信号处理算法而设计的。 - The Design Scheme of Motion Estimation Chip's Cache Architecture and It's Simulation Using FPGA
运动估计芯片的缓存设计策略及FPGA验证 - An ARM-based wireless LAN MAC system on chip architecture
一种基ARM7的无线局域网MAC片上系统架构 - Design of high performance SoC supporting CCD image sensor, and the basic chip architecture, the principle of image processing components and the implementation of the related algorithms, and its low power policy were presented.
介绍了支持CCD图像传感器的高性能SoC芯片的设计，芯片基本结构，与图像处理相关的功能部件的工作原理以及相关算法的硬件实现方法，以及相关的低功耗策略。 - A new smart card chip architecture was developed with very high security for information security systems.
为适应信息安全系统的要求，提出一种高安全性的智能卡芯片结构，并进行了设计实现。 - The principle of test bus is analyzed and general chip test architecture based on test bus is presented in the dissertation.
本文详细分析了测试总线的原理，并给出基于测试总线的通用芯片测试结构。 - The chip uses a reconfigurable architecture and very long instruction words ( VLIW) to optimize the complex functions.
芯片使用可重构体系结构和超长指令字（VLIW），优化了高复杂度函数。 - Design and Implementation of Cryptogrammic Chip Based on Reconfigurable Architecture
基于可重组体系结构的密码芯片设计及其实现 - In terms of design and application of chip, performance of proposed architecture models is compared.
从芯片设计和应用的观点，对各种结构模型进行了性能比较。 - So, the Single Chip Multiprocessor ( SCMP) architecture which integrate many simple microprocessors on one chip will soon be an efficient way to increase the performance of microprocessor with the improvements in semiconductor technology.
因此，随着半导体工艺技术的飞速发展，在一块芯片上集成多个相对简单的处理器的单芯片多处理器（SCMP）结构将是一条提高处理器性能的有效途径。 - A chip test architecture based on test bus is analyzed in the paper, and test scheduling in SOC is explained. Finally, the design of the chip test controller is presented, which is capable of carrying out test scheduling.
文章分析了基于测试总线的芯片测试结构，详细阐述了SOC设计中测试调度的概念，给出了一种能够灵活实现各种测试调度结果的芯片测试控制器的设计。 - With the development of integrated circuits technology, more and more resources are available on chip. Multi-core architecture design has become the main trend.
随着集成电路的发展，工艺技术的演进，芯片的集成度越来越高，多核结构迅速成为了处理器设计和发展的趋势。 - Paper will explains the Ethernet Routing chip processing algorithms, the internal bus system architecture, and chip architecture and related design and test methods.
论文中将讲解以太网路由芯片的处理算法，内部总线系统的结构，以及芯片架构和相关设计与测试方法等。 - We also proposed a kind of switch chip architecture with dual-channel ports and distributed arbitrators.
提出了采用双通道端口，分布式调度方式的交换芯片体系结构。 - A typical CMP ( Chip Multi-Processor) architecture often has a shared L2 cache and lower storage hierarchy. Sharing the L2 cache allows high cache utilization and avoids duplicating cache hardware resources.
在典型的多核处理器（CMP，Chipmulti-Processor）体系结构中，多个处理器核共享二级高速缓存，这种方式不仅能够提高高速缓存的利用率，还能避免存储器硬件资源的浪费。 - DSP chip is harvard architecture. And it is preferred tool to rapidly accurately deal with digital signal by means of peculiar hardware architecture and load-store.
DSP芯片采用哈佛结构，以独特的硬件体系以及指令体系迅速成为实时数字信号处理的首选工具，强大的数据处理功能使其广泛应用于通信领域。 - Thirdly, in order to solve the different requirements of the ECC application platform, the high-performance and the area and energy-constrained chip architecture are proposed.
再次，针对高性能和面积能耗约束下的两个不同领域的ECC的应用需求，提出了不同的芯片结构和实现方案。 - Chip Multi-core ( CMP) architecture has become the mainstream of processor design today.
片上多核已经成为当今处理器设计的主流。 - Third, verification platform design, this verification platform is based on the hardware and software co-verification and transaction authentication methods and simulation, full consideration of the SoC chip bus architecture that is common, so the reusability of the platform is very good.
第三，进行验证平台设计，这款验证平台是基于软硬件协同验证和事务及仿真的验证方法，充分考虑了SoC芯片的共性即总线结构，因此平台的可重用性非常好。 - Single chip multi-processor architecture ( CMP-Chip Multiprocessor) was hot spots in this area.
单片多处理器结构（CMP-ChipMultiprocessor）又是该领域中备受关注的问题。 - In addition, itis found that the spatial coherence of the light beams is related to its chip architecture of the multi-chip LEDs.
另外我们发现大功率多芯红光LED辐射光的空间相干性与其芯片分布有关。 - Asynchronous Network-on-Chip become the mainstream asynchronous chip interconnects architecture for next-generation chip systems because of its scalability, high modularity, high concurrency, clock localization and other advantages.
异步片上网络的高可扩展性、高模块化、高并发性、时钟本地化等优势使其成为下一代片上系统的主流互连架构。